1. Field of the Invention
The present invention relates to high-density semiconductor memories, particularly those having memory cells exhibiting diode-like conduction characteristics, and more particularly, to a three-dimensional passive element memory array and support circuits useful therewith.
2. Description of Related Art
Three-dimensional cross-point memory arrays achieve high density, but also must deal with several attributes of such a dense structure. There is a large capacitance loading on both the word lines and bit lines, and significant capacitive coupling between such lines in the array. Moreover, particularly with memory cells (i.e., memory elements) that include diodes, there are frequently large leakage currents between unselected bit lines and unselected word lines within the array.
These characteristics make sensing a memory cell in the array more difficult. The large capacitance loading on a selected bit line delays the development of a voltage signal on the selected bit line, causing long sense delays. This is especially true in diode arrays because the current available from each memory cell is usually very small. The leakage current of half-selected cells (i.e., a cell having one of its terminals connected to a selected word or bit line and its other terminal connected to an unselected line) detracts from the signal on the selected bit line. Also, developing a signal on a particular bit line may couple noise into adjacent bit lines, which reduces the sensing margins available and detracts from reliable sensing.
Another characteristic of such a memory array structure is the coupling between a selected bit line and all the unselected word lines crossing over the selected bit line. Because the steering elements in such memory cells are diodes or some other highly asymmetric steering devices, the unselected word lines and unselected bit lines are frequently biased at voltages which impart a reverse bias voltage across the unselected memory cells. Leakage currents may consequently flow between the unselected bit lines and unselected word lines during sensing, and may result in small voltage perturbations on the unselected word lines. Even these small voltage variations may couple very strongly into the bit line being sensed, and make sensing more difficult.
All of these are especially problematic in high density, large capacity memory arrays because the fan out on the memory lines, particularly the bit lines, may be as large as 512 or more and the cell current is usually very small. The coupling capacitance between word lines and bit lines is particularly high in a memory array with a rail-stack structure that has an antifuse memory cell above and below each rail-stack cross-point. Such memory structures are described in U.S. Pat. No. 6,034,882 to Mark G. Johnson, et al., and U.S. patent application Ser. No. 09/560,626 by N. Johan Knall, filed Apr. 28, 2000 and the continuation-in-part thereof, U.S. patent application Ser. No. 09/814,727, filed on Mar. 21, 2001. Memory arrays having antifuse memory cells incorporating diode-like structures (either before or after programming) are significantly affected by these characteristics.
Currently, such memories are limited in their performance and may have lower internal signal margins which can potentially cause significant manufacturing difficulty. There remains a need for improved circuit structures and methods for sensing a memory cell in a high density memory array in which these undesirable characteristics are present.
An improved sensing method biases a selected bit line at a particular voltage, and the current through the selected memory cell is sensed while the selected bit line voltage is generally maintained at the particular voltage. In a preferred embodiment particularly suitable for an antifuse memory cell, the bias on a selected bit line is changed by 1 volt or more relative to its bias when previously unselected. The particular voltage for the selected bit line is preferably chosen to be substantially equal to the unselected word line voltage to substantially eliminate leakage current through half-selected memory cells on the selected bit line. By biasing the unselected word lines and bit lines in accordance with the invention, negligible leakage currents flow to or from the selected word line and bit line, and the bit line current which is sensed arises largely from only the current through the selected memory cell.
In other embodiments, the voltage clamped bit line sensing may be combined with a noise detection line in the memory array, to reduce the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having bit lines on more than one layer includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
In yet other embodiments, a noise detection line may be even more useful in memory arrays using voltage variation on the bit line sensing, rather than clamped bit line sensing. Different aspects of the invention may be advantageously used alone or in combination.